In very large scale integrated (VLSI) circuit devices, several wiring layers are required to connect together the active and/or passive elements in a VLSI semiconductor chip. The interconnection structure consists of thin conductive lines separated by insulation in one layer or level and connected through vias or studs from contacts of the elements of the semiconductor chip or to a similar layer in another level of interconnections. This interconnection structure is similar to a transmission line in that there is a propagation delay of the signals being transmitted in these wiring layers. The delay is referred to as RC delay because it is a result of the resistance (R) of the material of the wire and the capacitance (C) between adjacent wires. With the trend of higher and higher levels of integration in semiconductor devices to ultra large scale integrated (ULSI) circuits, the space or gap between the wires or conductive lines to be filled with insulation is becoming extremely narrow between some of the conductive lines, such as those that are about 0.5 microns and smaller. Such a narrow space or gap between conductive lines increases the capacitance and places greater demands on the insulating properties of the insulation between such conductive lines. Capacitance (C) is the product of dielectric constant (DC) of the insulating material times the area (A) of the opposing faces of the conductive line divided by the distance (D) between the conductive lines. With a decrease in distance (D), the capacitance (C) increases. Since signal delay of signal transmitted on the conductive line is controlled by the RC constant, an increase in capacitance (C) degrades the performance of the integrated circuit.
At the present state of the art, the insulating material used to fill these gaps is a silicon containing compound, such as silicon dioxide, which has a dielectric constant (DC) of between 3.5 and 4.0. A vacuum has a perfect dielectric constant (DC) and is the basis for the measurement of the dielectric constant of other materials. For example, air and other insulating gases have a dielectric constant (DC) of slightly greater than 1, but less than 1.1. Air has a dielectric constant of 1.00059 and oxygen (O.sub.2) has a dielectric constant of 1.000523. The use of insulating material with dielectric constants (DC) lower than 3.5 in the narrow gap will lower the capacitance (C) and offset the increase caused by the smaller distance (D) between adjacent conductive lines. Attempts have been made to use organic insulating materials, such as polyimides which have a DC of between 3.2-3.4, but these materials are hydroscopic and any absorbed moisture can potentially cause corrosion of metal lines. Other possible insulating materials are boron nitride (BN.sub.x) and fluorinated silicon oxide (SiO.sub.x F.sub.y), but they also have dielectric constants above 3 and by themselves cannot achieve a lower dielectric constant.
In addition to the demands placed on the insulating property of the insulation between the conductive lines, these narrow gaps of about 0.5 microns and smaller make it much more difficult to deposit the insulating material into the gaps so that the gaps may not be completely and properly filled. In addition, when the height of the conductive line is increased, this increased height makes it still more difficult to fill, especially when the aspect ratio is 2 to 1 or greater with a gap distance of 0.5 microns or smaller. Aspect ratio is the height (h) of the conductive line divided by the distance (d) or gap between the conductive lines. It is pointed out in U.S. Pat. No. 5,124,014 to Pang-Dow Foo et al. that when the gap or distance (d) is less than the (h) of the conductive line, it is difficult to fill uniformly. U.S. Pat. No. 5,275,977 to Otsubo et al. confirms this problem and the inventors of both patents set the same objective for their processes; namely, the formation of the insulating film free of voids.
The disclosure in the Foo et al. patent describe a method for forming void free insulating layers between the conductive lines and it suggests that, from a detrimental standpoint, voids will form under certain conditions. However, this patent fails to recognize the advantage of voids surrounded by the insulating material in narrow gaps between conductive lines.
However, Ser. No. 08/478,315, filed Jun. 7, 1995, Ser. No. 08/481,906 filed Jun. 7, 1995 and Ser. No. 08/481,030 filed Jun. 7, 1995 and assigned to the same assignee do recognize the advantage of large voids surrounded by insulating material and describe and claim processes for creating a continuous void between at least narrow conductive lines.